A Delay Fault Test Scheme Based on Socillator Test In Boundary-Scan Environment

• Main Authors: Tek-Jau Tan, 陳德昭
• Other Authors: Chung-Len Lee
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/72578207831889267184

碩士 === 國立交通大學 === 電子工程系 === 88 === Delay fault testing in system-on-chip is difficult and the cost becomes increasingly higher. Boundary-scan is a standard and commonly used test scheme for ICs. In this thesis, we propose a test scheme to test the delay fault within the system-on-chip by using a modified boundary-scan structure. The main idea of this testing scheme is to provide an oscillation signal with the pulse width equal to the circuit maximum delay length and to observe the output transition before the next transition comes. This test architecture includes: an oscillation source generator (socillator), which could also be the system clock; a modified boundary-scan cell which can be randomly accessed from a primary-input and a primary-output from which we wish to apply tests, and a detector. We applied this scheme to some benchmark circuits and discuss the clock skew problem in practical applications. Furthermore, simulation and analysis on pattern generation for socillator test is done with this scheme.