A Delay Fault Test Scheme Based on Socillator Test In Boundary-Scan Environment
碩士 === 國立交通大學 === 電子工程系 === 88 === Delay fault testing in system-on-chip is difficult and the cost becomes increasingly higher. Boundary-scan is a standard and commonly used test scheme for ICs. In this thesis, we propose a test scheme to test the delay fault within the system-on-chip by...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72578207831889267184 |