Design of IDDQ Testable Low-Power High-Speed PLAs and Comparators, and Testing of Single-Ended SRAM and LCD Drivers
博士 === 國立中山大學 === 電機工程學系 === 88 === In this thesis, we present a low-power high-speed CMOS circuit implementation of NOR-NOR PLA using a single-phased clock. Buffering static NAND gates are inserted between the NOR planes to erase the racing problem and shorten the duration of glitches such that th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91291675892909897342 |