Feature Scale Simulation of Copper Deposition for IC Interconnection
碩士 === 國立清華大學 === 化學工程學系 === 88 === Because the trenches or vias of IC interconnect are very tiny and have large aspect ratio, how to deposit copper without void formation is very important. Development of numerical method from FDM、FEM to BEM or even Free-Element Method enable us to get approximate...
Main Authors: | Bang-hao Wu, 吳邦豪 |
---|---|
Other Authors: | Chi-Chao Wan |
Format: | Others |
Language: | en_US |
Published: |
2000
|
Online Access: | http://ndltd.ncl.edu.tw/handle/13959864307753170832 |
Similar Items
-
Analysis of Anisotropic Copper Electroplating for IC Interconnects
by: Bang-Hao Wu, et al.
Published: (2003) -
The application of contact displacement on copper interconnect for ic process
by: 陳志弘
Published: (2002) -
Investigation of Electroless Copper Deposition for Interconnection
by: Ming-Chan Lu, et al.
Published: (2000) -
The study of applying displacement reaction to copper interconnect for IC process
by: Wen-chih Chen, et al.
Published: (2001) -
Design and implementation of Chip-to-Chip Interconnect ICs
by: Cheng-Che Wu, et al.
Published: (2010)