Sensitivity analysis for VLSI layout using Voronoi diagram
碩士 === 國立清華大學 === 資訊工程學系 === 88 === Although VLSI fabrications increase their requirement for product yield, the existing layout optimization algorithms for yield enhancement are ineffecient in circuit sensitivity measurement. Therefore, this thesis presents an analysis method to measure the layout...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/07451210780314819857 |