study on low dielectric constant material in ULSI technology applications
碩士 === 國立清華大學 === 電子工程研究所 === 88 === As the ULSI circuits are scaled down, the linewidth and spacings between metal interconnect also are made smaller, transmission delay is primarily caused by the parasitic resistance and capacitance(RC) along the metallic lines. There are two principle methods of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04227607164441762018 |