| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 88 === The integration of copper and porous SiO2 were investigated. First, we fabricated porous SiO2 sample with different H2O/TEOS ratio to determine the optima deposition condition of the film. Secondly, the electroless plating copper/TaN or TaSi/porous SiO2/Si systems were studied to understand the thermal stability. For Cu-damascene technology, we manufactured capacitor with various combination of inter metal dielectric multilayer (Cu / TaN / Porous SiO2 / Si3N4 / Si，Cu/TaN/Peoxide
/ Porous SiO2 / Si3N4 / Si, and Cu / TaN / Si3N4 / Porous SiO2 / Si3N4 / Si )
.Elliposmeter, C-V ,and I-V were employed to study n, k, the thermal stability, and conduction mechanism. From the above measurement, we found the sample added with PEoxide or Si3N4 are better then the sample only with porous SiO2. Furthermore, at the interconnect resistance (Cu-line with damascene structure) against stress induced migration under 175oC storage for 7 hours with different cooling rate were measured with time. The larger stress induced resistance was found to be influenced by the cooling rate.
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