A Built-In Self-Test Design for All Digital Phase-Locked Loop
碩士 === 國立清華大學 === 電機工程學系 === 88 === Locking the frequency and phase between external and internal clocks, the phase-locked loops (PLLs) are fundamental elements in microelectronic systems. Traditionally, the analog PLL is designed for this task and the problem is that digital circuits suc...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/76886452498649911781 |