Low-Power and Low Phase-Error Phase-Locked Loop Design
碩士 === 淡江大學 === 電機工程學系 === 88 === Phase-locked loop (PLL) is the component broadly used in various field of integrated circuits. Phase-locked loop is generally used in clock recovery of communication system and frequency synthesizer of wireless communication system. Recently, owing to the broadly u...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09852958189496753741 |