THE DESIGN OF 1.5V CMOS CURRENT-MODE PIPELINE ANALOG-TO-DIGITAL CONVERTER
碩士 === 大同大學 === 電機工程研究所 === 88 === The design of a low voltage, 10-bit, current mode analog-to-digital converter (ADC) is proposed in this thesis. The converter operates under 1.5V supply voltage and has differential inputs. The circuits of the pipelined stages are implemented by the modified refere...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33225698390717345960 |