| Summary: | 碩士 === 大同大學 === 電機工程研究所 === 88 === The design of a low voltage, 10-bit, current mode analog-to-digital converter (ADC) is proposed in this thesis. The converter operates under 1.5V supply voltage and has differential inputs. The circuits of the pipelined stages are implemented by the modified reference non-restoring algorithm such that parts of the digital correction circuit can be embedded into the stages of ADC. In the entire ADC, we use 12-stage pipelined architecture. The modified reference non-restoring algorithm is used in the stages 1-6 and stages 7-12, respectively. According to the algorithm, the operations of sample-and-hold (S/H), multiplication by 2, addition, and subtraction are achieved by two or three S/H circuits in one stage. Then, the result of operation in one stage is converted into the digital signal by comparator. The 12-bit digital signal derived from 12 stages is further transferred into the digital correction circuit to produce 10-bit output. The simulation shows that the input range of this ADC is -50μA~50μA, sampling frequency is 143 kHz, and power consumption is 58mW.
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