Reduced-Complexity Equalizer Design
碩士 === 國立雲林科技大學 === 電子工程與資訊工程技術研究所 === 88 === This thesis aims at the development of various equalization methods for efficient VLSI realization, including 1. Time-domain equalization for asymmetric digital subscriber line (ADSL), 2. Reduced-complexity equalization via convolut...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21907212384809887119 |