DESIGN AND IMPLEMENTATION OF A 1.8-V 500-MHZ CMOS ADDLL
碩士 === 國立中正大學 === 電機工程研究所 === 89 === In this thesis, a new all digital delay locked loop (ADDLL) is proposed. The key features of this work are described as following: 1.Utilizing the two-step-approaching algorithm with coarse and find delay line, it can efficiently reduce the...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/70338355691705849834 |