| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 89 === In this thesis, a new all digital delay locked loop (ADDLL) is proposed. The key features of this work are described as following:
1.Utilizing the two-step-approaching algorithm with coarse and find delay line, it can efficiently reduce the phase lock in time.
2.The digital controlled current starved delay cell is adopted in the fine tune delay line for achieving lower jitter performance, when the whole loop enter the maintenance state.
3.To detect the phase difference for narrow pulse signal, a modified phase detector is proposed.
The proposed ADDLL has been fabricated with a 4-b × 4-b pipelined multiplier and a narrow pulse generator in the TSMC 0.35-μm CMOS process. This test chip has been measured with only 72-ps jitter in a 400 MHz, 1.8 V. From this design application, we confirm that this ADDLL can successfully work with a real digital clocking system. The total transistor number of our ADDLL is 1012 and core size is 340-μm × 290-μm.
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