| Summary: | 碩士 === 國立中興大學 === 資訊科學研究所 === 89 === BIST has emerged as a promising solution to the SOC testing problem. Most Test Pattern Generators (TPGs) used in BIST generate pseudorandom test patterns, which have low correlation between consecutive patterns and thus maximize power consumption in the circuit under test. This may damage the tested chips, as well as create reliability problem if the BIST is to be used frequently in system test.
This thesis proposes a new adjustable TPG structure that is targeted to reduce the switching activity during BIST test sessions.The proposed TPG structure consists of two parts, a LFSR and a Counter. The LFSR is driven by a slow clock whose speed is 1/2k of the normal clock, which is used to drive the Counter.
The proposed method is flexible, in that designers can select appropriate test structure for the given level of switching activity. The experimental results show that a 22%-84% reduction in switching activity can be achieved with no loss of fault coverage and the test length is about 10%-120% comparing with the original test sequence.
|
|---|
