Structural Precomputation Design for Low Power

• Main Authors: Paul Shyu, 徐玉龍
• Other Authors: Sying-Jyan Wang
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/77543755763805296704

碩士 === 國立中興大學 === 資訊科學研究所 === 89 === As the VLSI process technology continuously improves in recent years, the operational speed of a chip increased dramatically, and the number of transistors in a chip also increases greatly as expected. However, as the requirement for portable devices grows, we should pay much more attention to the power consumption in a circuit rather than it’s speed and area, and the need for low power is now evident in the circuit design. In applications like mobile phones, notebook computers, digital camera and so on, the low power consumption is one of the most important design considerations. We may have to sacrifice circuit performance and area to reduce power consumption, but it’s now acceptable since we just want to have a longer operating time of the device. In the thesis, we try to find out the best precomputation logic from a circuit by calculating a power-saving metric, which is determined from the structural analysis of the circuit’s information like net probability and savable net weight count. As a result, we can decrease the transition count in a circuit by controlling the input registers with the precomputation logic we found.