High Speed All Digital Phase-Locked Loop
碩士 === 國立中興大學 === 電機工程學系 === 89 === Abstract This thesis describes the architecture and design of a high speed all digital phase-locked loop (ADPLL), which uses sample and encode method to decide DCO operation model and frequency region of the input signal in 16 levels. The met...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37411327694764982533 |