8-bit CMOS Subranging Analog-to-Digital Converter
碩士 === 國立交通大學 === 電子工程系 === 89 === The thesis describes a 3.3V, 8-bit, 50MS/s analog-to-digital converter. The input voltage range is 0V~1.024V. The A/D converter is implemented by the subranging architecture, including coarse comparators, fine comparators, reference voltage generator, di...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45230657531375243871 |