On Layout-Driven Automatic Multiplier Generation
碩士 === 國立交通大學 === 電子工程系 === 89 === This thesis presents an automatic layout-driven multiplier generator. The cell-based delay model, rather than the XOR-based model, is used for timing estimation and the wire delay is also considered in the synthesis process. The timing optimization, by c...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82533470548817097587 |