| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 89 === In this thesis, we have fabricated Schottky barrier (SB) MOSFET on SOI wafers. SB MOSFET employs silicide source/drain in lieu of ion implanted source/drain. So it is simple in processing, well suited for low temperature process. Further, it can operate both as n- and p-channel transistors (i.e., ambipolar). However, traditional SB MOSFET suffers from extremely large leakage current inherent in metal-semiconductor Schottky junction and therefore poor on/off current ratio, which severely restricted its application to mainstream integrated circuits.
In this study, we have proposed and demonstrated new SB MOSFET devices that incorporated the field-induced-drain (FID) structure in an effort to reduce the large leakage current. Since FID can effectively reduce the high field in drain-side and induce the extension drain under the offset length, so the large leakage current can be effectively reduced and the device performance greatly improved. In order to understand on/off current ratio in more detail, we have investigated the effects of sub-gate bias and drain offset length on the resultant device characteristics. By studying devices with a series of long and short channels, we obtained the on/off current ratio for n- and p-channel devices to be 1E6 and 1E8, respectively. In this thesis, we used nickel silicide for source/drain. Since nickel silicide’s Schottky barrier height for electrons is about 0.7 eV larger than that for holes (0.41 eV), so the performance of n-channel operation is expected to be inferior to that of p-channel operation.
In the output characteristics, when VG and VD are large, n-channel device appeared reduction of drain current, the so-called called negative differential conductance (NDC). This is believed to be due to the source-side hot electron injection, causing electron trapping in the gate oxide. The resultant threshold voltage increase causes a reduction in the drain current. NDC is not observed in the p-channel operation, because the barrier height of holes to oxide is 4.7 eV, which is larger than that of electrons to oxide (i.e., 3.2 eV). It is worth noting that NDC phenomenon, though undesirable for normal transistor operation, could be potentially utilized as an efficient programming source for future low-power non-volatile memory (NVM) applications.
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