Process Optimization of Trench-Gate for Power MOSFET

• Main Authors: Pei-Chieh Liu, 劉沛潔
• Other Authors: Mao-Chieh Chen
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/09013082451126348830

碩士 === 國立交通大學 === 電子工程系 === 89 === Power MOSFET is characterized by a low on-resistance and high blocking voltage characteristics. The basic structure of power MOSFET consists of an epitaxial layer for voltage blocking and a drain electrode at the substrate contact. In the conventional vertical double diffused MOSFET, the on-resistance and packing density are limited by the horizontal channel of the device. The trench gate MOSFET, has a much improved on-resistance and packing density because of its vertical channel, however, it has a much complicated fabrication process. This thesis investigates the process optimization of the trench gate power MOSFET. The characteristics of the trench gate power MOSFET are closely related to the quality of gate oxide grown on the side wall of the trench. In particular, the quality of gate oxide at trench corners is of critical importance to the performance of the device. Rounding of the trench corners indicates the improvement of the device characteristics. In this thesis, two schemes are investigated with regarded to the rounding of the trench corner, namely, sacrificial oxidation prior to the gate oxidation and rapid thermal annealing (RTA) in hydrogen ambient prior to the gate oxidation. Moreover, oxidation conditions are investigated with respect to the improvement of gate oxide quality.