BIST for ADCs/DACs Linearity Testing
碩士 === 國立中央大學 === 電機工程研究所 === 89 === In this thesis, a new test methodology of BIST for on-chip ADC-DAC pair linearity testing is proposed. The on-chip digital signal processing unit and micro processing unit are used as test sources for calculating the test results. Hence, the on-chip...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/50510196128988417436 |
| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 89 === In this thesis, a new test methodology of BIST for on-chip ADC-DAC pair linearity testing is proposed. The on-chip digital signal processing unit and micro processing unit are used as test sources for calculating the test results. Hence, the on-chip test resources are fully used for our testing methodology. The test circuits are added as few as possible to prevent performance degradation of the overall system. To reduce the influence of system noise, the statistical methodology of oversampling is used. The proposed BIST scheme is ease of control and analysis.
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