VLSI Implementation and IP Design of RAM-Based Lempel-Ziv Data Compression
碩士 === 國立東華大學 === 資訊工程學系 === 89 === My thesis describes a novel Lempel-Ziv-Based(LZ) data compression chip with a pipelined parallel architecture for text comparing, encoding, and transferring for wireless communication system. Based on pipeline algorithm and systematic design methodolog...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65524655456872061766 |