An Enhanced Built-In Self-Test Complier for Multiple Memory Cores in System-on-Chip
碩士 === 國立清華大學 === 電機工程學系 === 89 === Memory testing is becoming the dominant factor in testing a System-on-Chip (SoC), with the rapidly growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-tes...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20715425108954611631 |