| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 89 === Testing and diagnosis are becoming important issues in system-on-chip (SoC) development while more and more embedded cores are integrated into single chips. We propose a built-in self-test and self-diagnosis scheme for embedded SRAMs and CAMs. It supports manufacturing test as well as diagnosis for design verification and yield improvement. With low hardware cost, our
memory BIST can handle various types of SRAM and CAM including pipeline and multi-port. In additional, a test scheduling methodology and a BIST compiler is also implemented, which aims
on reducing the testing time as well as test development time. To simplify the routing and reduce the test time of the proposed BISD circuit, a hamming syndrome compression scheme is also proposed. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size blocks. The average compression ratio is reduced to about 9% assuming 16-bit blocks.
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