A Hierarchical Test Access Mechanism for SoC and the Automatic Test Development Flow
碩士 === 國立清華大學 === 電機工程學系 === 89 === In recent years, using reusable cores, i.e., pre-design Intellectual Property (IP) blocks, to shorten the time-to-market for new ICs has become the most popular design methodology. In order to prevent test development from becoming the bottleneck in the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/52649334879069723163 |