A PLL-based CMOS Frequency Synthesizer
碩士 === 國立海洋大學 === 電機工程學系 === 89 === This thesis describes a 5V 240MHz~730MHz CMOS phase-locked loop (PLL), which is composed of a phase/frequency detector (PFD),a charge pump (CP),a low pass filter (LF),a voltage controlled oscillator (VCO) and a frequency divider (F...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94061021667640519903 |