Low Power and Low Voltage CMOS VLSI Cache Circuit Designs
博士 === 國立臺灣大學 === 電機工程學研究所 === 89 === In this thesis, new circuits and structures of cache memories suitable for low-power and low-voltage applications are described. In Chapter 2, the fundamental theory of cache memory is overviewed. In Chapter 3, a 1-V 128-kb four-way set-associative C...
Main Authors: | Perng-Fei Lin, 林鵬飛 |
---|---|
Other Authors: | James B. Kuo |
Format: | Others |
Language: | zh-TW |
Published: |
2001
|
Online Access: | http://ndltd.ncl.edu.tw/handle/92974344879434407429 |
Similar Items
-
Circuit Techniques Suitable for Low-Voltage CMOS VLSI
by: Stanley Bo-Ting Wang, et al.
Published: (2000) -
Low voltage, low power CMOS analog circuit design techniques for mobile, portable VLSI applications /
by: Hung, Chung-Chih
Published: (1997) -
Low-power digital CMOS VLSI circuits and design methodologies
by: Khellah, Muhammad M.
Published: (2006) -
Low-power digital CMOS VLSI circuits and design methodologies
by: Khellah, Muhammad M.
Published: (2006) -
Direct Bootstrapped Circuit Techniques Suitable for Low-Voltage CMOS VLSI
by: pcchen, et al.
Published: (2002)