| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 89 === Because routing is performed at the very end of the design process, if the routing of a design is badly performed, the design tasks previously done before routing may be iterated again to solve the routing problem. This often incurs a delay for time-to-market. In order to increase the probability of having a successful routing, routing planning should be performed early. This thesis develops a simple methodology to perform post placement routability analysis. The methodology is based on the vertical and horizontal wiring densities calculated for each of the detailed routing graph vertexes by taking into account the blockages formed by cell pins, prerouted wires, etc. The routability analyzer is used to tune chip area and the number of routing layers. The experimental results show that it can accurately estimate the number of routing layers for a chip but can not accurately predict the chip area. It is yet to find out an effective method to tune chip area.
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