The Architecture of Reconfigurable Critic Neural Network Controller
碩士 === 國立中正大學 === 電機工程研究所 === 90 === The objective of this thesis is to implement the architecture of Reconfigurable Critic Neural Network Controller in an IC chip. This architecture is principally designed based on the CMAC with a computation power of a 32-bit CPU. The architecture includes two par...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76770944548264741148 |