An All-Digital Phase-Locked Loop with Fast power-on and Wakeup Mechanism
碩士 === 國立中正大學 === 電機工程研究所 === 90 === ABSTRACT- A new architecture for the CMOS all-digital phase-locked loop (ADPLL) with fast power-on and wake-up designs is presented in this thesis. For fast power-on operation, a frequency predictor and a phase-error measurement circuit...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24851268189419655372 |