A Timing-Driven Hierarchical Partitioning Algorithm for VLSI Circuits
碩士 === 中原大學 === 資訊工程研究所 === 90 === A timing-driven hierarchical partitioning algorithm (HPA) for VLSI circuits is proposed. The HPA partitions a circuit to several partition blocks while maintaining the hierarchy of the circuit. It uses a cost function which combines net-cut, path-weight, and area...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60632372557898156996 |