A Timing-Driven Hierarchical Partitioning Algorithm for VLSI Circuits
碩士 === 中原大學 === 資訊工程研究所 === 90 === A timing-driven hierarchical partitioning algorithm (HPA) for VLSI circuits is proposed. The HPA partitions a circuit to several partition blocks while maintaining the hierarchy of the circuit. It uses a cost function which combines net-cut, path-weight, and area...
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| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60632372557898156996 |
| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 90 ===
A timing-driven hierarchical partitioning algorithm (HPA) for VLSI circuits is proposed. The HPA partitions a circuit to several partition blocks while maintaining the hierarchy of the circuit. It uses a cost function which combines net-cut, path-weight, and area of each module. It prevents the critical paths crossing through partition block boundaries. An exhaustive search approach is utilized to find the minimal cost for different number of partitions. An area constraint of module is added to the HPA. It helps the HPA to obtain area balanced partition results in shorter CPU time. The program has been tested on several industrial circuits. Comparing to the flattened circuits, it has the result of a shorter circuit path delay with balanced size of partition blocks. These blocks may also be implemented in a shorter time. Experimental results are presented.
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