Low-Jitter Dual-Loop Nested Delay-Locked Loop
碩士 === 華梵大學 === 機電工程研究所 === 90 === This thesis describes a dual-loop nested delay-locked loop (DLL), which is different from the conventional one. Nested topology architecture achieves low-jitter performance. The dual-loop DLL for skew-free distribution of clocks, can generate equally spaced time fo...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13319664707199253337 |