| Summary: | 碩士 === 華梵大學 === 機電工程研究所 === 90 === This thesis describes a dual-loop nested delay-locked loop (DLL), which is different from the conventional one. Nested topology architecture achieves low-jitter performance. The dual-loop DLL for skew-free distribution of clocks, can generate equally spaced time for the duty-cycle adjustment. Comparing with the conventional one, the proposed DLL keeps the same benefits of conventional DLL’s such as good jitter performance. In this thesis, the voltage-controlled delay line (VCDL) achieves wide-range operation with little gain variation. The chip has been fabricated with TSMC 0.35-mm 1p4m N-well CMOS process. When the supply voltage is 3.3V, over the operating frequency range of 100~300MHz, the measured rms and peak-to-peak jitter are less than 5.8ps and 58ps, respectively. When the input clock is 300MHz, the power dissipation of the circuit is 41mw.
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