Low-Jitter Dual-Loop Nested Delay-Locked Loop

碩士 === 華梵大學 === 機電工程研究所 === 90 === This thesis describes a dual-loop nested delay-locked loop (DLL), which is different from the conventional one. Nested topology architecture achieves low-jitter performance. The dual-loop DLL for skew-free distribution of clocks, can generate equally spaced time fo...

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Bibliographic Details
Main Authors:	Yi-Zhen Huang, 黃怡貞
Other Authors:	Ching-Yuan Yang
Format:	Others
Language:	zh-TW
Published:	2002
Online Access:	http://ndltd.ncl.edu.tw/handle/13319664707199253337

id	ndltd-TW-090HCHT0657017
record_format	oai_dc
spelling	ndltd-TW-090HCHT06570172015-10-13T17:39:44Z http://ndltd.ncl.edu.tw/handle/13319664707199253337 Low-Jitter Dual-Loop Nested Delay-Locked Loop 具有較低信號抖動之雙迴路巢狀式延遲鎖定迴路設計 Yi-Zhen Huang 黃怡貞碩士華梵大學機電工程研究所 90 This thesis describes a dual-loop nested delay-locked loop (DLL), which is different from the conventional one. Nested topology architecture achieves low-jitter performance. The dual-loop DLL for skew-free distribution of clocks, can generate equally spaced time for the duty-cycle adjustment. Comparing with the conventional one, the proposed DLL keeps the same benefits of conventional DLL’s such as good jitter performance. In this thesis, the voltage-controlled delay line (VCDL) achieves wide-range operation with little gain variation. The chip has been fabricated with TSMC 0.35-mm 1p4m N-well CMOS process. When the supply voltage is 3.3V, over the operating frequency range of 100~300MHz, the measured rms and peak-to-peak jitter are less than 5.8ps and 58ps, respectively. When the input clock is 300MHz, the power dissipation of the circuit is 41mw. Ching-Yuan Yang 楊清淵 2002 學位論文 ; thesis 84 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 華梵大學 === 機電工程研究所 === 90 === This thesis describes a dual-loop nested delay-locked loop (DLL), which is different from the conventional one. Nested topology architecture achieves low-jitter performance. The dual-loop DLL for skew-free distribution of clocks, can generate equally spaced time for the duty-cycle adjustment. Comparing with the conventional one, the proposed DLL keeps the same benefits of conventional DLL’s such as good jitter performance. In this thesis, the voltage-controlled delay line (VCDL) achieves wide-range operation with little gain variation. The chip has been fabricated with TSMC 0.35-mm 1p4m N-well CMOS process. When the supply voltage is 3.3V, over the operating frequency range of 100~300MHz, the measured rms and peak-to-peak jitter are less than 5.8ps and 58ps, respectively. When the input clock is 300MHz, the power dissipation of the circuit is 41mw.
author2	Ching-Yuan Yang
author_facet	Ching-Yuan Yang Yi-Zhen Huang 黃怡貞
author	Yi-Zhen Huang 黃怡貞
spellingShingle	Yi-Zhen Huang 黃怡貞 Low-Jitter Dual-Loop Nested Delay-Locked Loop
author_sort	Yi-Zhen Huang
title	Low-Jitter Dual-Loop Nested Delay-Locked Loop
title_short	Low-Jitter Dual-Loop Nested Delay-Locked Loop
title_full	Low-Jitter Dual-Loop Nested Delay-Locked Loop
title_fullStr	Low-Jitter Dual-Loop Nested Delay-Locked Loop
title_full_unstemmed	Low-Jitter Dual-Loop Nested Delay-Locked Loop
title_sort	low-jitter dual-loop nested delay-locked loop
publishDate	2002
url	http://ndltd.ncl.edu.tw/handle/13319664707199253337
work_keys_str_mv	AT yizhenhuang lowjitterdualloopnesteddelaylockedloop AT huángyízhēn lowjitterdualloopnesteddelaylockedloop AT yizhenhuang jùyǒujiàodīxìnhàodǒudòngzhīshuānghuílùcháozhuàngshìyánchísuǒdìnghuílùshèjì AT huángyízhēn jùyǒujiàodīxìnhàodǒudòngzhīshuānghuílùcháozhuàngshìyánchísuǒdìnghuílùshèjì
_version_	1717783525388713984

Low-Jitter Dual-Loop Nested Delay-Locked Loop

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