Design of Low-Power Precomputation-Based Fully Parallel Content addressable Memory
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === This paper presents a novel VLSI architecture for a fully parallel precomputation-based content addressable memory (PB-CAM) with low-power, low-cost, high-speed, and high-reliability features. This design is based on a precomputation skill that not only save...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86g37f |