Dispatching Rules for Possibly Delayed Lots In an IC Foundry

• Main Authors: Wen-Yang Tseng, 曾文揚
• Other Authors: Muh-Cherng Wu
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/54948971923481811130

碩士 === 國立交通大學 === 工業工程與管理系 === 90 === In order to improve the on-time delivery of IC foundries, this research develops a dynamic dispatching rule that gives higher priority to thee possibly delayed lots. The basic idea is by giving an alarm whenever the progress of a manufacturing wafer lot is behind its lot control schedule. The lot control schedule defines the target progress of each operation of the lot. Based on the lot information provided by the lot control schedule system, we adjust the dispatching priority of wafer lot. Simulation results show that the proposed dynamic dispatching rule can effectively reduce the number of delay lots if the lot control schedule is appropriately defined.