Low Power DFT by Scan Chain Reordering
碩士 === 國立交通大學 === 資訊工程系 === 90 === Scan-Chain insertion is widely used in design for testability (DFT) technique to test sequential circuit. The test pattern could propagate to the Circuit Under Test (CUT) through the scan chain serially to reduce needed data ports. However, the power of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61513460572016464150 |