| Summary: | 博士 === 國立交通大學 === 資訊科學系 === 90 === As technology advances, the circuit size in modern VLSI design increases dramatically. To handle the increasing design complexity, hierarchical designs and IP modules are widely used for design convergence, which makes floorplaning more important than ever. The major objective of floorplanning/placement is to allocate the modules of a circuit into a chip to optimize a predefined cost metric such as area, timing, routability, etc. The realization of floorplanning/placement relies on a representation which describes geometric relations among modules. The representation has a great impact on the feasibility and complexity of floorplan designs. Thus, it is of particular significance to develop an efficient, effective, and flexible representation for floorplan/placement designs. In this dissertation, we first propose the concept of the P*-admissible representation, and then present two graph based representations, namely Transitive Closure Graph (TCG) and Transitive Closure Graph-Sequence (TCG-S) representations for general floorplans. Since the geometric relations of modules are transparent to the two representations and their operations, we can easily use TCG and TCG-S to deal with arbitrarily shaped modules and various placement constraints, such as the boundary constraint, the pre-placed constraint, and the symmetry constraint. Unlike most of previous works, our approaches can guarantee the feasibility in each perturbation in handling these problems. Also, the methods are very simple and can be implemented easily.
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