Ultra-Shallow Junction Formation for Nano MOS Devices Using Amorphous Silicon Capping Layer

• Main Authors: Huang-Chun Wen, 溫凰君
• Other Authors: Tan Fu Lei
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/80161201359276452221

碩士 === 國立交通大學 === 電子工程系 === 90 === In this thesis, we have proposed a new ultra-shallow junction formation method for nano-MOS technology applications. As device dimension scales down, the short channel effects become more serious. Formation of ultra-shallow junctions is essential to minimizing punch-through and short channel effects. This thesis presents a method to fabricate ultra-shallow junctions using present ion implantation and rapid thermal annealing techniques without requirement of low energy implant equipments. Diffusion from implanted amorphous silicon (DIA) is performed by junction implant through an amorphous capping layer; the amorphous layer thus acts as a surface solid diffusion source during annealing. A thin oxide is deposited to serve as etching stop layer beneath the amorphous layer. This bilayer amorphous-oxide structure enables easy removal of the amorphous layer and provides good process control and device reliability. By using amorphous silicon layer as the diffusion source for junction formation, implant defects are reduced. Defect-free ultra-shallow junctions can be formed. DIA junctions are also co-implanted with F to observe the effect of F on junction characteristics. Finally, DIA junctions combined with Ti capped Ni silicide processes have been fabricated. The DIA structure has been found to reduce periphery junction defects. These junctions exhibit good electrical and junction characteristics suitable for the future MOS technology.