A DFT Scheme for PLL Fault Diagnosis
碩士 === 國立交通大學 === 電子工程系 === 90 === This thesis proposes a DFT scheme for phase-locked loop diagnosis. PLL plays a very import role in communication systems nowadays, such as low-jitter PLL-based frequency synthesizer、clock recovery and synchronization. For the PLL, to improve the yield an...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94662713534571818117 |