On Multiplier Synthesis under Error Constraint
碩士 === 國立交通大學 === 電子工程系 === 90 === The thesis presents an automatic error-controlled hardware-configurable multiplier generator. The determination of the hardware of a multiplier is based on the error constraint given by users. With allowing some rounding errors, a significant reduction i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91933819419727069661 |