Interconnect Optimization for Deep Submicron Technology
博士 === 國立交通大學 === 電子工程系 === 90 === As revealed by the 1999 international technology roadmap for semiconductors, technology will soon shrink into below 0.1 micrometer and the chip complexity will be over 200 million transistors. For such large and complex design, timing closure and design convergence...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2002
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Online Access: | http://ndltd.ncl.edu.tw/handle/47345907133992880378 |