The Fast Lock ADDLL System Uses Asynchronous Time Mapping Tracking (ATMT)
碩士 === 國立交通大學 === 電機與控制工程系 === 90 === Clock skew is an increasing concern for high speed circuit designing. This paper describes a simple concept for realizing a fast all digital delay locked loop (ADDLL) circuit that operates at high frequency between 300Mhz and 800MHz and with fast lock...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00873638561030171885 |