Study of Ferroelectric Devices Integration

• Main Authors: Xian-Cong Lain, 連憲聰
• Other Authors: Dong-Po Wang
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/56297562359216040053

碩士 === 國立中山大學 === 物理學系研究所 === 90 === Abstract In recent years ferroelectric memory devices have attracted much attention from the viewpoint of the next generation of highly integrated circuits. Research and development in dynamic random access memory (DRAM) using high dielectric constant films are extensive. However, DRAM is volatile memory, and it is desirable that nonvolatile memory should be developed. There are mainly two kinds of ferroelectric nonvolatile memories: a memory cell using a ferroelectric storage capacitor, and metal-ferroelectric-(insulator)-semiconductor FET (MFISFET). Especially, the latter is superior among memory devices since the memory is read out nondestructively. In practice, however, there are many challenges which have held back the progress in that direction, a major one being the difficulty of making an electrically switchable ferroelectric thin film on Si with good interface properties and long retention time. To overcome these problems, buffer layers are usually inserted between the ferroelectric layer and silicon substrate. The electrical properties of the MFIS memories with stacked gate configuration of ferroelectric Pt/SrBi2Ta2O9/Si3N4/p-Si (100) were investigated. 245nm-thick SBT thin films were spin-coated on the Si3N4/Si substrate followed by 1 min. rapid thermal crystallization annealing at the temperatures regime of 700~800℃. In an attempt to operate memory at low voltage with sufficient large memory window, various ultra thin Si3N4 buffer layers in thickness of 3.5, 2, and 0.9nm were employed. The Si3N4 buffer layers were deposited by means of LPCVD with the exception of surface nitridation for 0.9nm SixNy thin film. From the results of C-V measurements, the memory window can be as large as 0.8V at the bias amplitude of 5 V for the sample with 0.9 nm SixNy buffer layer and 750℃ annealing temperature. Complete perovskite crystalline structure can also be affirmed by the spectra of X-ray diffraction measurements. The leakage current, which plays a very important role in the data retention, of Pt/SBT (245nm)/ Si3N4 (0.9nm)/p-Si (100) is as low as 2.5 x 10-8 A/cm2 at 200kV/cm. The 1010 write cycles and greater than 2hr retention time can be achieved. Optimization and scaling of SBT thin films are believed to be effective in pursuing extremely low voltage operation, high-density and liable 1T nonvolatile ferroelectric random access memories.