An FIFO Memory Design for Data Exchange Bus and Analog Front-end of Digital Cordless Headset Baseband Controller
碩士 === 國立中山大學 === 電機工程學系研究所 === 90 === Three different chip design topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of an FIFO memory design for 8-to-32 data exchange bus. An FIFO memory architecture is proposed to be utiliz...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/52387511557110418680 |