Performance-Driven Clustering for Hierarchical FPGA Architecture
碩士 === 國立清華大學 === 資訊工程學系 === 90 === In this thesis, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We present an efficient three-level clustering heuristic algorithm for delay minimi...
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| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63699945688968202579 |