The Integration of a Testable CMOS Image Sensor with Ideal Logarithmic Output Response
碩士 === 國立清華大學 === 電機工程學系 === 90 === In this thesis, a CMOS image sensor (CIS) with ideal logarithmic response designed and fabricated in 0.35μm 1P4M n-well CMOS process is presented. A system level simulation environment that can simulate the images captured by an image sensor is also dev...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2002
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/27372041195481841220 |