Gate-Delay Fault Diagnosis Using The Inject-And-Evaluate Paradigm
碩士 === 國立清華大學 === 電機工程學系 === 90 === Abstract For many high-performance IC designs, the verification of timing is essential yet challenging. After manufacturing, certain defects may cause some chips to fail in timing. In order to improve the manufacturing yield and shorten the t...
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| Format: | Others |
| Language: | zh-TW |
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2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87681765918728540197 |